In recent years, to meet the demand on realizing a high density for electronic devices, a carrier tape, which can accommodate semiconductor elements in a film tape and can be assembled on a liquid crystal panel or a printed circuit board, has been widely used.
A conventional technique of such a carrier tape will be explained in the following.
Symbol 103 in FIG. 11(a) represents a film tape. An adhesive is coated on the surface of the film tape in advance to form adhesive layer 154.
Said film tape 103 is punched to form hole 115 (FIG. 11(b)). Metal foil (metal film) 108 is then laminated on adhesive layer 154 (FIG. 11(c)). In the aforementioned hole, there are other holes not shown in the figure and used when film tape 103 is cut or used for positioning. However, hole 115 shown in FIG. 11 is called a device hole for accommodating semiconductor elements. The inner surface of metal foil 108 is subjected to a roughening treatment to improve the adhesion to film tape 103. Therefore, the bumps and dips on the inner surface of the metal film are exposed in the device hole.
When the tape is dipped in an etching solution for a chemical polishing treatment to degrease and smoothen the surface after metal foil 108 is laminated, the exposed portion of metal foil 108 is etched. In this case, not only the surface of metal foil 108, but also the inner surface of metal foil 108 exposed from hole 115, are etched and become smooth.
When the original thickness of metal foil 108 and the etching quantities on the surface and the inner surface are taken as a, b, and c, respectively, the thickness of portion 161 of metal foil 108 positioned on film tape 103 becomes a-b, while the thickness of portion 162 positioned on device hole 115 becomes even smaller, that is, a-(b+c) (FIG. 11(d)).
Subsequently, resist film 166 is formed on the whole inner surface of film tape 103, with resist film 165 being formed on the surface of etched metal foil 108. Resist film 165 is patterned as shown in FIG. 11(e). When the tape is dipped in an etching solution at this time, metal foil 108 is etched from opening portions 168 of resist film 165. In this way, patterned metal film wirings 110.sub.1 and 110.sub.2 are formed on film tape 103 and resist film 166 on the inner surface, respectively (FIG. 11(f)).
Subsequently, when a peeling treatment is performed to remove patterned resist film 165, first wirings 111 are formed from metal film wirings 110.sub.1 on film tape 103. When resist film 166 on the inner surface is removed at the same time to expose device hole 115, one end of each metal film wiring (110.sub.2) on resist 166 on the inner surface is fixed on film tape 103, while the other end is suspended over device hole 115 to form second wiring 112 called an inner lead (FIG. 11(g)).
After a protective film is formed on a portion of each first wiring 111 of said carrier tape 102, semiconductor elements are accommodated in the device hole, and the electrodes on the semiconductor elements are electrically connected to second wirings 112. Subsequently, the semiconductor elements are potted and covered by resin, followed by performing electrical experiments. When the carrier tape is assembled on a liquid crystal panel, the electrode on the liquid crystal panel is connected to a portion of the first wiring after film tape 103 is cut for each semiconductor element.
Because carrier tape 102 in the conventional technique is formed by the aforementioned manufacturing operation, first wiring 111 is different from second wiring 112 in thickness. Because metal foil 108 is generally etched by means of wet etching, the etching reaction is carried out from opening portions 168 in a direction parallel to the surface of the carrier tape, resulting in a large side etching quantity. Consequently, it is difficult to realize fine patterning in the thick portions of metal foil 108.
FIG. 12 is the plane view of said carrier tape 102. Second wirings 112 used for connection to the electrodes on the semiconductor elements are arranged at small pitches on the periphery of device hole 115.
Symbol 116 in FIG. 12 represents a lead hole. It is formed at the same time that film tape 3 is punched to form device hole 115. Wirings 113 are formed at large pitches on said lead hole. When the wirings are connected to the electrodes on a printed circuit board, a heating jig is applied from the outer surface or the inner surface to perform a soldering connection.
Symbols 121 represent pads for a test performed on film tape 103 at the same time that first wirings 111 are formed. These pads are used for the electrical testing of the semiconductor elements. Symbol 122 represents an electrode portion of each first wiring 111 connected by an electroconductive resin to the electrodes formed on a liquid crystal panel.
Because the electrodes on the semiconductor elements accommodated in device hole 115 are formed at small intervals, it is necessary to use second wirings 112 at small pitches. On the other hand, because the electrodes are arranged at relatively large intervals on the liquid crystal panel, portions 122 of first wirings 111 connected to the panel are formed at large pitches.
Because the wiring pitch requested by first wirings 111 is different from that requested by second wirings 112, a pitch-converting portion 109 is formed by first wirings 111. When portions 122 of first wirings 111 connected to the liquid crystal panel are connected to the portions of second wirings 112 connected to the semiconductor elements, respectively, first wirings 111 in pitch-converting portion 109 on the side of portions 122 connected to the liquid crystal panel have to be formed at the pitches as large as those among portions 122. On the other hand, first wirings 111 in pitch-converting portion 109 on the side of second wirings 112 have to be formed at pitches that are as small as those among the second wirings.
However, as the number of pins of the semiconductor elements is increased, the pitches among second wirings 112 used for element connection become even narrower. On the other hand, because the bottom surface of first wirings 111 is subjected to a roughening treatment to improve the adhesion to film tape 103, the etching time for performing fine patterning in pitch-converting portion 109 becomes short when pitch-converting portion 109 is formed from first wirings 111 using the conventional technique. When this takes place, the metal film of first wirings 111 cannot be completely etched, and the remaining metal film is left over on adhesive layer 154. Consequently, the portions connected to second wirings 112 are shorted and defective products are manufactured, which is a problem.
The purpose of this invention is to solve the aforementioned problem of the conventional technique by providing a type of carrier tape that can be used for semiconductor elements with many pins.